1. Technical Field
The invention relates generally to integrated circuit (IC) design, and more particularly, to a method, system and program product enabling a netlist for modeling of technology dependent back-end-of-line (BEOL) process variation.
2. Background Art
In the integrated circuit (IC) design industry, parasitic extraction is used to model capacitance and resistance values of structures within an integrated circuit (IC) design. Numerous entities provide parasitic extractors, such as Star (available from Synopsis) or Calibre (available from Mentor Graphics), that are capable of this function. Typically, the parasitic extraction provides a list of structures and their connection points which are connected in each net of the IC design, which is referred to as a netlist, and their corresponding parasitic capacitance and resistance values. These locations or structures are identified within the IC design as a pair of resistors (e.g., R1, R2) and a capacitor (e.g., C1). Each of the resistors and the capacitor are identified by a pair of nodes, e.g., a net to which they belong, between which each extends. For example, a capacitor C1 may be located between nodes identified as: 140:13936 and 146:13901, and may have a capacitance of 1.26475e-19 Farads (F). Each resistor R1, R2 shares one of the nodes with capacitor C1. For example, a resistor R1 may share node 146:13901 with capacitor C1 and have a resistance value of 13.6585, and another resistor R2 may share node 140:13936 with capacitor C1 and have a resistance value of 0.08815. Note, that the capacitor and resistor identifications are arbitrary. Each resistor may also include a variety of comments that aid in identifying the resistor. For example, each resistor may include a level comment to identify the level at which it terminates, e.g., metal level 2. For example, resistor R1 may include a level comment L=21, and resistor R2 may include a level comment L=23. In that example, capacitor C1 represents a capacitance that extends between levels because the level indications are not the same, but that is not always the case. That is, if the level comments are identical, the capacitor represents a capacitance that extends laterally. Each resistor may also include a corresponding width comment and length comment of the structure which it represents, e.g., wire.
One shortcoming of conventional parasitic extractors is that they do not allow for Monte Carlo modeling of the capacitance and resistance values based on a particular technology without generating three different netlists, i.e., one each for the maximum value scenario, nominal value scenario and minimum value scenario. In a Monte Carlo model, values are specified as a distribution, typically a Gaussian distribution, with a specified nominal value and a multiple standard deviation to a maximum value and a minimum value. Unfortunately, generating three different netlists is very time consuming and expensive.
There is a need in the art for a solution to one or more of the problems of the related art.